1. Field of the Invention
The invention relates generally to a method of manufacturing a flash memory device, and more particularly to, a method of manufacturing a flash memory device capable of improving not only the resistance of a word line but also the film quality of a dielectric film and a gate oxide film in a peripheral circuit region.
2. Description of the Prior Art
Generally, a flash memory device is mainly divided into a cell region and a peripheral circuit region. The peripheral circuit region is divided into a high voltage transistor region and a low voltage transistor region.
As the integration level of semiconductor devices becomes higher, reduction of the device is inevitably required as the area occupied by a unit device is reduced. Due to this, there are problems that the resistance in the wire such as a word line is increased and the device is higher integrated. In order to improve the performance of the device even though the device is reduced, it is required that the film quality of a dielectric film of an ONO (Oxide-Nitride-Oxide) structure, an insulating film applied to other devices, and the like be preferably formed. In particular, in a cell gate of a stack gate flash EEPROM, it is a general practice that metal-silicide such as tungsten-silicide (WSiX) has been used in order to reduce the resistance of the word line.
FIG. 1Axcx9cFIG. 1D are cross-sectional views of a conventional flash memory device for explaining a method of manufacturing the device.
Referring now to FIG. 1A, a device isolation film 12 is formed in a semiconductor substrate 11 in which the cell region and the peripheral circuit region (including the high voltage transistor region and the low voltage transistor region) are defined. Then, a tunnel oxide film 13 and a first polysilicon layer 14 are sequentially formed on the entire surface of the semiconductor substrate 11 in which the device isolation film 12 is formed. Next, the first polysilicon layer 14 and the tunnel oxide film 13 are removed by an etch process using a first photoresist pattern (not shown) through which the device isolation film 12 in the cell region is exposed and the first photoresist pattern is then removed.
In the above, the tunnel oxide film 13 is formed in thickness of 80 xc3x85xc2x14 xc3x85 and the first polysilicon layer 14 is formed in thickness 600 xc3x85xc2x160 xc3x85.
Referring now to FIG. 1B, a dielectric film 15 is formed on the entire structure including the first patterned polysilicon layer 14. The dielectric film 15 and the first polysilicon layer 14 in the peripheral circuit region are removed by an etch process using a second photoresist pattern (not shown) in which the cell region is covered. Then, the second photoresist pattern is removed.
In the above, the dielectric film 15 has an ONO structure in which a lower oxide film is deposited in thickness of 40 xc3x85xc2x14 xc3x85, a nitride film is deposited in thickness of 60 xc3x85xc2x16 xc3x85 and an upper oxide film is deposited in thickness of 40 xc3x85xc2x14 xc3x85.
Referring to FIG. 1C, a process of oxidizing a gate in the high voltage transistor, a process of forming a third photoresist pattern (not shown) through which the low voltage transistor region is exposed, a wet etch process of removing oxide, a process of removing the third photoresist pattern and process of oxidizing the gate in the low voltage transistor are sequentially implemented to form gate oxide films 16a and 16b in the high voltage transistor region and the low voltage transistor region, respectively. A second polysilicon layer 17 is formed on the entire structure in which the gate oxide films 16a and 16b are formed.
In the above, the high voltage gate oxide film 16a is formed in thickness of 125 xc3x85xc2x16 xc3x85 and the low voltage gate oxide film 16b is formed in thickness of 55 xc3x85xc2x13 xc3x85. The second polysilicon layer 17 is formed in thickness of 700 xc3x85xc2x170 xc3x85 wherein the second polysilicon layer 17 is formed by first depositing doped polysilicon in thickness of about 600 xc3x85 and then depositing undoped polysilicon in thickness of about 100 xc3x85.
Referring now to FIG. 1D, a metal-silicide layer 18 is formed on the second polysilicon layer 17 and a hard mask layer 19 is formed on the metal-silicide layer 18. Next, general processes are performed
In the above, the metal-silicide layer 18 is formed by depositing a material such as tungsten silicide in thickness of 1500 xc3x85xc2x1150 xc3x85. The hard mask layer 19 functions to protect the gate from processes such as an etch process, etc. that is subsequently performed and is formed by sequentially depositing a PE-TEOS film, a PE-the nitride film and an ARC nitride film. At this time, the PE-TEOS film is deposited in thickness of 300 xc3x85xc2x130 xc3x85,  the PE-the nitride film is deposited in thickness of 2000 xc3x85xc2x1200 xc3x85 and the ARC nitride film is deposited in thickness of 1200 xc3x85xc2x1120 xc3x85.
The flash memory device explained by reference to the drawings was described by taking a stack gate flash EEPROM of 0.18 xcexcm technology as an example. Therefore, it should be noted that the numerical limit is set based on 0.18 xcexcm technology.
If the flash memory device is manufactured by the above conventional method, there occur the following problems.
First, as, only the device isolation film 12 portion in the cell region in the first polysilicon layer 14 etched using the first photoresist pattern as an etch mask is open, the difference in a topology is generated in this portion. Thus, a seam 100 is generated in the metal-silicide layer 18 that will become the word line along with the second polysilicon layer 17, as shown in FIG. 1d. The seam 100 is further expanded through a subsequent annealing process and the resistance of the word line is thus significantly increased. An increase in the resistance of the word line causes to reduce the speed of the device. In general, an EDR target (Electrical Design Rule Target) has a sheet resistance in the word line of 7.6xcexa9. On the contrary, the sheet resistance in the word line where the seem 100 is generated as above is over 45xcexa9.
Second, after the dielectric film 15 such as the ONO structure is formed, the dielectric film 15 and the first polysilicon layer 14 in the peripheral circuit region are removed by an etch process using the second photoresist pattern and the second photoresist pattern is then removed. At this time, when the second photoresist pattern is removed, loss of about 5 xc3x85 is generated on the surface of the dielectric film 15 and the film quality of the dielectric film 15 is transformed by plasma that is applied when the second photoresist pattern is removed. Therefore, the quality of the dielectric film 15 as an insulating material is degraded and the capability to store information that is most important in the flash memory device is resultantly degraded.
Third, when the gate oxide films 16a and 16b are formed in the peripheral circuit region, a pre-cleaning process is performed in order to improve the film quality of the gate oxide films 16a and 16b. In this case, there is a problem that loss of the dielectric film 15 such as the ONO structure is caused to degrade the film quality of the dielectric film 15. Meanwhile, if the pre-cleaning process is not performed in order to prevent degradation in the film quality of the dielectric film 15, there is a problem that the film quality of the gate oxide films 16a and 16b is degraded.
The present invention is contrived to solve the above problems and an object of the present invention is to provide a method of manufacturing a flash memory device capable of improving not only the resistance of a word line but also the film quality of a dielectric film and a gate oxide film in a peripheral circuit region.
In order to accomplish the above object, a method of manufacturing a flash memory device according to the present invention, is characterized in that it comprises the steps of forming a device isolation film in a semiconductor substrate in which a cell region and a peripheral circuit region are defined; sequentially forming a tunnel oxide film and a first polysilicon layer on the entire surface of the semiconductor substrate; removing the first polysilicon layer and the tunnel oxide film to expose the device isolation film in the cell region; forming a dielectric film on the entire surface including the first polysilicon layer; forming an amorphous silicon layer on the entire surface including the dielectric film; etching the amorphous silicon layer to an extent that the dielectric film is not exposed; removing the amorphous silicon layer, the dielectric film and the first polysilicon layer in the peripheral circuit region; forming a gate oxide film in the peripheral circuit region; forming a second polysilicon layer on the entire structure including the gate oxide film; removing the second polysilicon layer in the cell region to expose the amorphous silicon layer in the cell region and the second polysilicon layer in the peripheral circuit region; forming a top polysilicon layer on the entire structure including the exposed amorphous silicon layer and the second exposed polysilicon layer; and forming a metal-silicide layer on the top polysilicon layer.